1. Field of the Invention
This invention relates generally to semiconductor capacitors and, more particularly, to semiconductor capacitors of the electrode-insulator-semiconductor type that can be used in combination with MOS devices for fabricating circuits with the MOS devices especially useful in MOS memory circuit applications such as dynamic random access memories.
2. Description of the Prior Art
In the past, various semiconductor capacitor structures have been developed in attempts to improve the ability of the capacitor structure to have greater reliability for use or a greater charge storage ability for given size of capacitor area.
One prior attempt to increase the capacitance of a semiconductor capacitor structure was to develop a sub-surface convoluted semiconductor region by diffusion which would thereby provide a greater PN function length because of the convoluted portion and thereby increase the capacitance of the semiconductor diffused capacitor for a given area size. However, this type of semiconductor capacitor structure was costly to fabricate because it required the formation of oxide patterns in the form of a grid configuration on the surface of the semiconductor region where the diffusion operation was to be performed in for fabricating the convoluted semiconductor capacitor structure. The extra oxide paterning step was obviously more costly which resulted in the increased cost necessary to produce this prior art type of semiconductor capacitor.
Another form of semiconductor capacitor that is very popular today and is used in many circuit designs with MOS devices is the semiconductor capacitor described in U.S. Pat. No. 3,519,897 that is assigned to the same assignee of this patent application. This particular semiconductor capacitor structure is very reliable due to the use of an inversion preventing highly doped barrier region around the semiconductor portion that serves as one plate of the capacitor structure. The reason for this highly doped barrier region around the capacitor's semiconductor region or plate is to provide a method for delimiting the inversion area around this semiconductor region and to prohibit any unintentional and undesired expansion of the inversion region caused by a potential source being applied to the electrode or plate on the dielectric layer located on a surface of the semiconductor region.
As the technology has developed and advanced, the demand has increased for developing new semiconductor capacitor structures that would not require fairly precise alignments, as is required in the above cited patent, where the electrode plate needs to be positioned and spaced so that the plates edges are within the diffused barrier region. Additionally, there was a need to develop a new type of semiconductor capacitor that would use doped regions within a substrate for creating both a high capacitance value and a reliable capacitor structure that could be used with an MOS device for various types of applications especially for use in a single device MOS memory cell to be used in dynamic random access memories.
Because of the need to minimize use of silicon real estate, it is important that the semiconductor capacitor structure would have a higher capacitance for a given area than previous semiconductor capacitor designs. It was also necessary to provide a semiconductor capacitor structure that could be used with the faster N channel MOS type devices which requires that the new semiconductor capacitor design be able to work well in a substrate of P- type conductivity.
Thus, there was a need to provide an improved semiconductor capacitor structure that would solve the above identified problems associated with prior semiconductor capacitor structures and would be compatible for integrated use with N channel MOS devices in single device random access memory cell designs.